Method of Forming a Thin Film Transistor

ABSTRACT

A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.

RELATED PATENT DATA

This patent resulted from a divisional application of U.S. patentapplication Ser. No. 12/135,761, filed Jun. 9, 2008, which resulted froma continuation of U.S. patent application Ser. No. 11/021,651, filedDec. 22, 2004, now U.S. Pat. No. 7,385,222, issued on Jun. 10, 2008,which is a continuation application of U.S. patent application Ser. No.09/902,277, filed Jul. 9, 2001, now U.S. Pat. No. 6,890,842 B2, issuedon May 10, 2005, which is a divisional application of U.S. patentapplication Ser. No. 09/837,645, filed Apr. 17, 2001, now U.S. Pat. No.6,344,376, issued on Feb. 5, 2002, which is a continuation of U.S.patent application Ser. No. 09/457,206, filed Dec. 7, 1999, now U.S.Pat. No. 6,238,957, issued on May 29, 2001, which is a continuation ofU.S. patent application Ser. No. 08/872,789, filed Jun. 10, 1997, nowU.S. Pat. No. 6,001,675, issued on Dec. 14, 1999, which is acontinuation of U.S. patent application Ser. No. 08/594,127, filed Jan.31, 1996, now U.S. Pat. No. 5,665,611, issued on Sep. 9, 1997.

TECHNICAL FIELD

This invention relates to thin film transistors and to methods offorming thin film transistors.

BACKGROUND OF THE INVENTION

As circuit density continues to increase, there is a corresponding driveto produce smaller and smaller field effect transistors. Field effecttransistors have typically been formed by providing active areas withina bulk substrate material or within a complementary conductivity typewell formed within a bulk substrate. Although the field effecttransistor feature size is reducing with advances in process technology,even greater packing density can be achieved by forming transistors inthin films deposited over insulating layers, such as oxide. Thesetransistors are commonly referred to as “thin film transistors” (TFTs).

With TFTs, a thin film of semiconductive material is first provided. Acentral channel region of the thin film is masked, while opposingadjacent source/drain regions are doped with an appropriate p or n typeconductivity enhancing impurity. A gate insulator and gate are providedeither above or below the thin film channel region, thus providing afield effect transistor having an active channel region formed entirelywithin a thin film as opposed to a bulk substrate.

The invention grew out of needs associated with TFTs and their usage inhigh-density static random access memories (SRAMs) and flat paneldisplays. A static memory cell is characterized by operation in one oftwo mutually exclusive and cell-maintaining operating states. Eachoperating state defines one of the two possible binary bit values, 0or 1. A static memory cell typically has an output which reflects theoperating state of the memory cell. Such an output produces a “high”voltage to indicate a “set” operating state. The memory cell outputproduces a “low” voltage to indicate a “reset” memory cell operatingstate. A low or reset output voltage usually represents a binary valueof 0, and a high or set output voltage represents a binary value of 1.

A static memory cell is said to be bi-stable because it has two stableor self-maintaining operating states, corresponding to two differentoutput voltages. Without external stimuli, a static memory cell willoperate continuously in a single one of its two operating states. It hasinternal feedback to maintain a stable output voltage, corresponding tooperating states of the memory cell, as long as the memory cell receivespower.

The operation of the static memory cell is in contrast to other types ofmemory cells, such as dynamic cells, which do not have stable operatingstates. A dynamic memory cell can be programmed to store a voltage whichrepresents one of two binary values, but requires periodic reprogrammingor “refreshing” to maintain this voltage for more than very short timeperiods. A dynamic memory cell has no feedback to maintain a stableoutput voltage. Without refreshing, the output of a dynamic memory cellwill drift towards intermediate or indeterminate voltages, effectivelyresulting in loss of data.

Dynamic memory cells are used in spite of this limitation because of thesignificantly greater packaging densities which can be attained. Forinstance, a dynamic memory cell can be fabricated with a single MOSFETtransistor, rather than the six transistors typically required in astatic memory cell. SRAM cell density can be maximized withthree-dimensional integration. For example, load transistors of the SRAMcell constitute TFTs which are folded over the bulk transistors. Becauseof the significantly different architectural arrangements and functionalrequirements of static and dynamic memory cells and circuits, staticmemory design has developed along a different path than has the designof dynamic memories.

Ongoing efforts in SRAM circuitry have brought about the development ofTFTs in an attempt to minimize space and for other advantageous reasonsassociated with TFTs. While the invention grew out of needs associatedwith TFTs of SRAM circuitry, the artisan will appreciate applicabilityof the invention to other types of circuitry. By way of example only,such include TFT-based liquid crystal or other active matrix displays,where a TFT can be used as a pass transistor in a pixel element and alsoin the driver circuitry.

One common material utilized as the thin source, channel and drain filmin a TFT is polysilicon. Such is comprised of multiple forms ofindividual single crystal silicon grains. The locations where twoindividual crystalline grains abut one another is commonly referred toas a grain boundary. Grain boundaries are inherent in polycrystallinematerials, such as polysilicon, as it is the boundaries which define thebreaks between individual crystal grains. The crystalline structurebreaks down at the grain boundaries, giving rise to a high concentrationof broken or “dangling” Si bonds. These dangling bonds “trap” carriersand give rise to potential barriers at the grain boundaries. Thesepotential barriers impede the flow of carriers in polysilicon, thusreducing conductivity compared to bulk silicon.

The grain boundary potential barrier height is proportional to thesquare of the dangling bond density, or “trap density”. The smaller thegrain size, the higher the trap density and thus the lower theconductance. In a TFT, the grain boundary potential barrier height inthe channel is controlled by the gate voltage, and hence theconductivity is a function of the gate voltage. The TFTs, however, havea lower drive compared to bulk transistors because of lower mobility inthe channel and higher threshold voltage to the larger trapconcentration.

The grain boundary trap concentration also affects the leakage currentof OFF-current in TFTs. In polysilicon or other polycrystalline TFTs,the presence of grain boundary traps at the drain end can dramaticallyincrease the leakage current in the presence of a “gate-to-drain”electric field. The increase in leakage results from either “thermionicfield emission” and/or “Poole-Frenkel” emission through the grainboundary traps. Accordingly, the greater the number of grain boundaries(i.e., the smaller the grain size), the greater the current leakagethrough the material. Greater current leakage means that more power isrequired to replace the leaking current to maintain an SRAM celltransistor in its desired powered-on state. Such leakage is particularlyadverse in laptop computers, where desired power consumption when acell's state is not being changed would be desired to be very low toextend battery life.

High density SRAMs (16 Mb or higher) typically require TFTs with low OFFcurrents (<50 fA) and high ON current (>5 nA) in order to obtainacceptable low standby leakage and high memory cell stability. Currentstate-of-the-art TFTs provide low standby current at the expense of ONcurrent, or at the expense of additional process complexity. One presentway of minimizing this current leakage at the cost of increased processcomplexity is by providing a “lightly doped offset” (LDO) region withinthe thin film. A lightly doped offset region is an elongated regionwithin the thin film which is positioned effectively between the channelregion and the drain region which is not under “direct” control of thegate fields, but rather is affected by the gate's “fringing fields”.Such a region provides a buffer zone for the electric field between thechannel and drain which minimizes leakage therebetween.

One prior art manner of contending with problems associated with grainsboundaries is to “passivate” such boundaries after their formation. Onetechnique involves exposing the thin film polycrystalline layer toatomic or plasma hydrogen, with the intent being to tie-up the danglingSi bonds at the boundaries with hydrogen. An alternate technique is toimplant fluorine into the thin film polycrystalline layer in an effortto produce silicon-fluorine bonds at the boundary interfaces. Asilicon-fluorine bond is much more desirable than a silicon hydrogenbond due to increased high temperature stability. However, the existingion implantation techniques of providing fluorine into a polycrystallinethin film is not without drawbacks. For example, the implantationundesirably damages the thin film layer and typically creates moredangling bonds inherent from the implantation process. Further, a largepercentage of the fluorine does not reach the grain boundaries, evenupon diffusion, and is therefore ineffective for the purpose ofpassivation, as ion implantation distributes the fluorine uniformlythroughout the grains and grain boundaries.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

FIG. 1 is a diagrammatic sectional view of a wafer fragment at oneprocessing step in accordance with the invention.

FIG. 2 is a view of the FIG. 1 wafer at a processing step subsequent tothat shown by FIG. 1.

FIG. 3 is a view of the FIG. 1 wafer at a processing step subsequent tothat shown by FIG. 2.

FIG. 4 is a view of the FIG. 1 wafer at a processing step subsequent tothat shown by FIG. 3.

FIG. 5 is a diagrammatic sectional view of another wafer fragment at oneprocessing step in accordance with the invention.

FIG. 6 is a diagrammatic sectional view of still another wafer fragmentat one processing step in accordance with the invention.

FIG. 7 is a view of the FIG. 6 wafer at a processing step subsequent tothat shown by FIG. 6.

FIG. 8 is a diagrammatic sectional view of still a further waferfragment at one processing step in accordance with the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

This disclosure of the invention is submitted in furtherance of theconstitutional purposes of the U.S. Patent Laws “to promote the progressof science and useful arts” (Article 1, Section 8).

In accordance with one aspect of the invention, a method of forming athin film transistor relative to a substrate comprises the followingsteps:

providing a thin film transistor layer of polycrystalline material on asubstrate, the polycrystalline material comprising grain boundaries;

providing a fluorine containing layer adjacent the polycrystalline thinfilm layer;

annealing the fluorine containing layer at a temperature and for a timeperiod which in combination are effective to drive fluorine from thefluorine containing layer into the polycrystalline thin film layer andincorporate fluorine within the grain boundaries to passivate said grainboundaries; and

providing a transistor gate operatively adjacent the thin filmtransistor layer.

In accordance with another aspect of the invention, a method of forminga thin film transistor relative to a substrate comprises the followingsteps:

providing a thin film transistor layer of polycrystalline material on asubstrate, the polycrystalline material comprising grain boundaries;

providing a sacrificial fluorine containing layer over thepolycrystalline thin film layer;

annealing the fluorine containing layer at a temperature and for a timeperiod which in combination are effective to drive fluorine from thefluorine containing layer into the polycrystalline thin film layer andincorporate fluorine within the grain boundaries to passivate said grainboundaries;

after annealing, etching the sacrificial layer from the polycrystallinethin film layer; and

providing a gate dielectric layer and a gate relative to the passivatedpolycrystalline thin film layer.

Referring to FIGS. 1-4 and initially to FIG. 1, a semiconductor waferfragment in process is indicated generally with reference numeral 10.Such comprises a bulk substrate region 12 and an overlying insulativelayer 14. A thin film transistor layer 16 of polycrystalline material isprovided relative to composite substrate 12/14. Such will comprise grainboundaries inherent in polycrystalline materials. A typical andpreferred material for layer 16 is polysilicon, with otherpolycrystalline materials, such as germanium and silicon-germanium, alsobeing contemplated.

A fluorine containing layer 18 is provided outwardly overpolycrystalline thin film layer 16. Layer 18 preferably contains suchfluorine as an excess of fluorine in the form of free or looselyassociated fluorine atoms. An example and preferred material for layer18 is WSi_(x) provided by chemical vapor deposition utilizing WF₆ andSiH₄ as precursors. The fluorine from the WF₆ precursor will desirablybe appreciably incorporated in layer 18 for use as described below. Anexample process for providing layer 18 by CVD using WF₆ and SiH₄ in amanner which maximizes incorporated fluorine includes WF₆ feed at 3sccm, Ar at 500 sccm, SiH₄ at 300 sccm, T at 400° C. and a pressure of 1Torr. Alternately by way of example only, fluorine containing layer 18might predominantly comprise elemental W having incorporated fluorine,such as by utilizing a CVD process also using WF₆ as a precursor.Regardless where layer 18 is to predominantly comprise W or a Wcompound, WF₆ is a preferred precursor for providing fluorine withinsuch layer.

Referring to FIG. 2, wafer fragment 10 and thereby fluorine containinglayer 18 is subjected to a suitable annealing temperature for a timeperiod which in combination are effective to drive fluorine fromfluorine containing layer 18 into polycrystalline thin film layer 16.Such fluorine will be incorporated within the grain boundaries topassivate said grain boundaries. The principal mechanism by which suchfluorine transports from layer 18 to 16 is understood to bepredominantly physical (diffusion), as opposed to by chemical action.Alternately but less preferred, such fluorine displacement from layer 18to layer 16 might occur by a chemical mechanism. However mostpreferably, the annealing temperature and time are selected to besufficiently great to drive fluorine from layer 18 into polycrystallinelayer 16, but also sufficiently low to prevent a chemical reaction oflayer 18 with layer 16.

For example where layer 18 predominantly comprises elemental tungsten,an annealing temperature is preferably less than 700° C. to prevent thetop or a substantial portion of layer 16 from being reacted with layer18 to form WSi_(x). Typical and example preferred annealing temperaturesfor a WSi_(x) or other as-deposited layer 18 which has reactionresistance with respect to polycrystalline material of layer 16 is fromabout 600° C. to 1000° C. for anywhere from 5 seconds (rapid thermalprocessing) to greater than one hour. The incorporated fluorine withinlayer 16 preferably forms Si—F bonds with the dangling bonded siliconatoms inherent at the grain boundaries.

Referring to FIG. 3 and after annealing, fluorine containing layer 18 ispreferably etched from outwardly of passivated polycrystalline thin filmlayer 16, thereby being sacrificial. An example etch chemistry wherelayer 18 predominately comprises WSi_(x) is a combination of hydrogenperoxide and ammonium hydroxide.

Referring to FIG. 4, subsequently a gate dielectric layer 20 isprovided, along with a gate 22 outwardly relative to passivatedpolycrystalline thin film layer 16. Source, drain, offset, Vt adjust, orother implants would ultimately be provided to produce the desired TFTconstruction. Such are not shown or otherwise described, as such do notconstitute aspects pertinent to the claimed invention.

The above described embodiment was described with reference to fluorinecontaining layer 18 being both sacrificial and provided after thin filmtransistor layer 16 was provided. FIG. 5 illustrates an alternateembodiment of a wafer fragment 10 a where a fluorine containing layer 18a is neither sacrificial nor provided after provision of a thin filmpolycrystalline layer. Like numerals from the first described embodimentare utilized where appropriate, with differences being indicated by thesuffix “a” or with different numerals. Here, fluorine containing layer18 a is provided intermediate underlying insulating layer 14 andoverlying thin film polycrystalline layer 16. If fluorine containinglayer 18 a were electrically conductive, a fluorine transmissiveelectrical insulating layer (i.e., a 50-100 Angstroms of SiO₂) can beprovided intermediate layers 18 a and 16. The selected anneal conditions(for example those described above) will effectively move fluorine atomsfrom layer 18 a into layer 16 to provide the passivating effect. Layer18 a would then remain after passivation.

Another alternate embodiment wafer fragment 10 b and associatedprocessing is described with reference to FIGS. 6 and 7. Like numeralsfrom the first described embodiment are utilized where appropriate, withdifferences being indicated with the suffix “b” or with differentnumerals. FIG. 6 is of the same essential composition as the fragment ofFIG. 1, but for provision of a buffering layer 25 intermediate thin filmtransistor layer 16 and fluorine containing layer 18. Buffering layer 25can be provided to provide etch selectivity of layer 18 relative to 16,and as may be desired to protect the outer surface of layer 16 relativeto contact with layer 18. An example and preferred material for layer 25is an insulating material, such as SiO₂ deposited to a thickness of fromabout 50 Angstroms to about 200 Angstroms. In such instance however,buffering layer 25 will be transmissive of fluorine atoms from fluorinecontaining layer 18 during the annealing step.

Referring to FIG. 7, fluorine containing layer is illustrated as havingbeen selectively etched relative to buffering layer 25 after driving ofthe fluorine atoms into layer 16. Buffering layer 25 would typicallysubsequently be etched, and processing continuing to occur as shown byFIG. 4 to produce a thin film transistor construction.

The above described embodiments were with respect to a top-gated thinfilm transistor construction. FIG. 8 illustrates yet another alternateembodiment whereby a bottom-gated thin film construction is provided.Like numerals from the first described embodiment are utilized whereappropriate, with differences being indicated by the suffix “c” or withdifferent numerals. Here, wafer fragment 10 c is illustrated as having abottom gate 22 c provided relative to an insulating layer 27, such asSiO₂. Gate dielectric layer 20 c and thin film transistor layer 16 c areprovided outwardly relative to layer 27 and gate 22 c. A fluorinecontaining layer 18 is provided outwardly of polycrystalline thin filmlayer 16 c for the annealing step. Also, a buffering layer could beprovided intermediate thin film transistor layer 16 c and fluorinecontaining layer 18.

Regardless and in all of the above described embodiments, a fluorinecontaining layer is provided operatively adjacent a polycrystalline thinfilm layer in a manner effective to enable an effective annealingtemperature and time to transfer fluorine atoms from the fluorinecontaining layer to the polycrystalline thin film layer. Further andregardless, in each of the above embodiments at some point a transistorgate is provided operatively adjacent the thin film transistor layer.Further, subsequent hydrogen passivation could also be conducted withoutdeparting from the principals and scope of the invention.

Thin film transistors produced according to the above describedembodiment have improved operating characteristics.

In compliance with the statute, the invention has been described inlanguage more or less specific as to structural and methodical features.It is to be understood, however, that the invention is not limited tothe specific features shown and described, since the means hereindisclosed comprise preferred forms of putting the invention into effect.The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A semiconductor construction comprising: a polycrystalline materialhaving grains and grain boundaries and having fluorine non-uniformlydistributed between the grains and the grain boundaries; afluorine-containing material operably adjacent the polycrystallinematerial, the fluorine-containing material comprising tungsten; and atransistor gate operably adjacent the polycrystalline material.
 2. Thesemiconductor construction of claim 1 wherein the polycrystallinematerial comprises germanium-silicon.
 3. The semiconductor constructionof claim 1 wherein the polycrystalline material and thefluorine-containing material are present on a substrate having aninsulative layer thereon.
 4. The semiconductor construction of claim 3wherein the insulative layer underlies both the polycrystalline materialand the fluorine-containing material.
 5. The semiconductor constructionof claim 1 wherein the at least some of the fluorine present at thegrain boundaries bonds with silicon.
 6. The semiconductor constructionof claim 1 further comprising a gate dielectric layer overlying thepolycrystalline material and the fluorine-containing material.
 7. Thesemiconductor construction of claim 6 wherein the transistor gateoverlies the gate dielectric layer.
 8. A semiconductor constructioncomprising: a passivated polycrystalline material layer, the passivatedpolycrystalline material layer being formed by a method comprising:providing a layer of polycrystalline material over a substrate, thepolycrystalline material having grains and grain boundaries; forming afluorine-containing layer proximate the layer of polycrystallinematerial; and transferring fluorine into the grain boundaries from thefluorine-containing layer to form the passivated polycrystallinematerial layer, the passivated polycrystalline material layer havingfewer dangling bonds than would occur had the fluorine present in thepassivated layer been provided by implanting.
 9. The semiconductorconstruction of claim 8 wherein the polycrystalline material comprisesat least one member of the group consisting of silicon and germanium.10. The semiconductor construction of claim 8 wherein the passivatedpolycrystalline layer has fluorine non-uniformly distributed between thegrains and the grain boundaries.
 11. The semiconductor construction ofclaim 8 wherein the polycrystalline material comprises silicon andwherein at least some of the fluorine present within the grainboundaries is bonded to Si atoms.
 12. The semiconductor construction ofclaim 8 wherein the passivated polycrystalline material layer isincorporated into a thin film transistor.